Role Overview :

We are seeking an experienced VLSI Verification Engineer with strong expertise in PCIe protocol to join our team. The candidate will be responsible for functional verification of high-speed interfaces, ensuring design correctness and compliance with industry standards.

Key Responsibilities :

- Develop and execute verification plans for PCIe-based IPs and subsystems.

- Create testbenches using SystemVerilog/UVM methodology.

- Perform simulation, debugging, and coverage analysis to ensure design quality.

- Work closely with design teams to understand specifications and resolve issues.

- Implement assertions, scoreboards, and monitors for protocol compliance.

- Analyze and report functional coverage metrics and improve test quality.

- Participate in code reviews and contribute to verification methodology improvements.

Required Skills :

- Strong knowledge of PCIe protocol (Gen3/Gen4/Gen5 preferred).

- Hands-on experience with SystemVerilog and UVM.

- Proficiency in simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).

- Experience in debugging waveform and log files.

- Familiarity with coverage-driven verification and assertion-based verification.

- Good understanding of digital design concepts and SoC/IP verification flows.

Preferred Skills :

- Exposure to C/C++ or Python scripting for automation.

- Knowledge of other high-speed protocols (e.g., Ethernet, USB, DDR).

- Experience with formal verification and emulation platforms.

- Familiarity with version control systems (Git, Perforce).

Education :

- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or Computer Engineering.

Soft Skills :

- Strong analytical and problem-solving skills.

- Excellent communication and teamwork abilities.

- Ability to work in a fast-paced environment and meet deadlines.