- Deep understanding of C, embedded programming, and hardware/software co-validation methodologies.

- Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts.

- Proven history of developing and executing verification and validation strategies for complex SoCs.

Essential Duties And Responsibilities :

- Ownership : End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure.

- Protocol Expertise : Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, IC, I3C, SPI, AXI, AHB, and APB.

- Emulation Experience : Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage.

- Testbench Proficiency : Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components.

- Simulation & Debug : Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis.

- Pre-/Post-Silicon Validation : Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases.

- Datapath Validation : Ability to understand and validate complex datapath flows of the controller, create datapath scenarios in SoC verification environments, and port them across pre-silicon and post-silicon environments.

- Post-Silicon Experience : Hands-on experience in post-silicon ASIC bring-up, validation, and debug.

- Firmware & HAL Development : Develop firmware, bare-metal tests, and Hardware Abstraction Layer (HAL) code to enable datapath, integration, and SoC-level validation and verification.

- Language Proficiency : Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development.

- Validation Infrastructure : Build and maintain validation infrastructure, including test content, regression automation, and lab equipment integration (oscilloscopes, analyzers, logic probes).

- Debug Expertise : Proficiency in debugging SoC issues across multiple domains (digital logic, firmware, timing, low-power, DFT) using JTAG, trace, waveform capture, and performance counters.

- Power & GLS Validation : Run and debug gate-level simulations, power-aware (UPF/CPF) validation, and validate ATE functional patterns.

- Performance & Stress Testing : Validate and verify performance bottlenecks, traffic generation, and corner-case stress scenarios at the SoC level.

- Verification Methodology : Apply advanced verification methodologies, including constrained-random, coverage-driven, and assertion-based verification to ensure design quality and completeness.

Updated Experience and Compensation :

- Experience : 5-8 years

- CTC : 39-45