RTL Design Engineer - System Verilog

Description :

Role : RTL Design Engineer RISC-V CPU Architecture

Location : Bangalore

Experience : 7+ Years

Education : Bachelors / Masters / Ph.D. in Electrical Engineering, Electronics, Computer Engineering, or a related field.

Key Responsibilities :

1. Micro-architecture Design & Specification:

- Define and develop detailed micro-architecture specifications for various RISC-V CPU components.

Design advanced CPU features such as :

- Branch prediction units

- Instruction scheduling mechanisms

- Register renaming logic

- Vector execution units

- Collaborate with architecture teams to translate high-level architectural concepts into detailed RTL specifications.

- Evaluate trade-offs between performance, power consumption, and silicon area (PPA).

2. RTL Development & Implementation :

- Lead and contribute to RTL development of CPU cores using Verilog/SystemVerilog.

- Develop highly optimized RTL designs ensuring compliance with timing, performance, and power targets.

- Implement CPU pipelines, instruction execution units, and datapath logic.

- Ensure design scalability and maintainability through modular RTL architecture.

3. CPU Architecture Evaluation & Benchmarking :

Analyze and benchmark different RISC-V core implementations, including :

- In-order cores

- Out-of-order cores

- Superscalar architectures

- Evaluate architectural performance using simulation and modeling tools.

- Work with performance modeling teams to validate architecture decisions against real workloads and performance metrics.

4. Virtualization & Security Enhancements :

- Implement and optimize hardware-assisted virtualization features within the CPU architecture.

- Integrate architectural extensions to support secure execution environments.

- Ensure compliance with security standards and implement hardware-level security mechanisms.

5. SoC Infrastructure & Fabric Integration :

Architect and integrate critical infrastructure elements required for SoC integration including :

- Bus protocols (AXI, CHI)

- Clocking architecture

- Reset and power management subsystems

- Collaborate with SoC integration teams to ensure smooth interoperability between CPU cores and system components.

- Work closely with clock, reset, and power design teams to optimize overall SoC efficiency.

6. End-to-End Design Flow Ownership :

- Participate in the complete CPU design lifecycle, including :

- Architectural exploration

- RTL implementation

- Functional verification

- Performance validation

- Physical design readiness

- Support integration with verification environments, simulation frameworks, and debug tools.

- Work closely with verification teams to ensure high coverage and design correctness.

7. Technical Leadership & Mentorship :

- Mentor and guide junior engineers in CPU architecture and RTL design best practices.

- Establish coding standards, design methodologies, and documentation practices across the team.

- Provide technical leadership in complex design challenges and architectural decision-making.