RTL Design Engineer - System Verilog

Description :

Key Responsibilities :

- RTL Design & Micro-Architecture

- Develop and implement micro-architecture specifications for complex SoC components.

- Design high-quality RTL using Verilog / SystemVerilog following best practices.

- Work on ARM-based ecosystem components including M7, Coresight, NIC, and AMBA interconnects.

SoC Integration & Debug :

- Integrate and debug SoC components within ARM-based environments.

- Work with AMBA protocols (AXI, AHB, APB) and system debug infrastructure.

- Understand and implement SoC peripheral interfaces such as QSPI, UART, GPIO, and others.

Static Checks & Synthesis :

- Develop and verify timing constraints, support synthesis, and ensure timing closure.

- Run and resolve issues related to Lint and CDC checks.

- Collaborate with physical design teams to ensure smooth handoff and execution.

Cross-functional & Vendor Collaboration :

- Coordinate with multiple IP vendors and internal IP teams to ensure quality and timely deliverables.

- Participate in design reviews, documentation, and cross-team technical discussions.

Required Skills & Experience :

- Minimum 8 years of experience in RTL design and SoC development.

- Strong expertise in ARM-based ecosystems (M7, Coresight, NIC, AMBA interconnects).

- Deep understanding of AMBA bus protocols and SoC debug infrastructure.

- Proficiency in Verilog / SystemVerilog, micro-architecture design, synthesis, and constraints.

- Experience with timing constraint development, Lint, and CDC analysis.

- Knowledge of SoC interfaces including QSPI, UART, GPIO, etc.

- Proven ability to work with multiple IP vendors and internal cross-functional teams.