Radiant Semiconductors - Design Verification Engineer - UVM/System Verilog

Description : Design Verification Engineer

Location : Bengaluru

Experience : 4 to 15 Years

Job Description :

The ideal candidate should have strong UVM knowledge and experience across high-speed protocols.

Key Responsibilities :

- Write functional coverage models based on DV plans

- Develop assertions and scoreboard-based checkers

- Analyze digital and functional coverage metrics

- Develop UVCs and UVM tests to close coverage gaps

- Work on protocols such as PCIe, UCIe, Ethernet, DDR, AMBA, and CPU

- Debug and close regressions effectively

Skills :

- SystemVerilog, UVM, Testbench development

- Functional Coverage, Assertions, Scoreboards

- PCIe / UCIe / Ethernet / DDR / AMBA / CPU protocols

- Debugging & regression closure

- Coverage-driven verification

- Strong problem-solving & communication