The Opportunity :

We are seeking a skilled and highly analytical PrimePower Design Engineer to join our team, focusing on comprehensive power analysis and optimization for cutting-edge ASIC SoC designs.

This role is critical for ensuring our products meet stringent low-power targets in advanced technology nodes (7nm and below).

Key Responsibilities :

- Comprehensive Power Analysis : Conduct detailed power analysis in both vector (simulation) and vector-less (activity-based) modes of ASIC SoC design.

- This must be performed across different design stages, ranging from RTL to the gate-level netlist.

- Flow Automation and Improvement : Actively contribute to the development, improvement, and automation of internal power analysis flows to enhance efficiency and accuracy.

- Optimization Feedback : Investigate areas of power inefficiency within the design and provide targeted, actionable feedback and solutions to the core design teams.

- Cross-Functional Collaboration : Work closely with the physical design team to optimize the clock tree, floorplan, and physical implementation based on power analysis results.

- Memory Optimization : Participate in memory power optimization initiatives through careful memory selection and analysis of memory traffic profiles.

- Communication : Clearly present technical results and findings to a wider audience and senior management in weekly meetings.

Minimum Qualifications :

- ASIC Flow Expertise : Proven experience with the RTL2GDSII design flow usage and development in advanced technology nodes (7nm and below).

- Low Power Signoff : Strong knowledge and practical experience with low power implementation and signoff techniques, including power gating, multiple voltage rails, and UPF/CPF (Unified Power Format/Common Power Format) usage.

- Power Analysis Tools : Mandatory hands-on experience in power analysis and reduction using PrimeTime PX / PrimePower (Synopsys tools) or equivalents.

- Scripting Proficiency : Mandatory proficiency in scripting languages such as Python and TCL for automation and flow development.

- Low Power Techniques : Deep familiarity with fundamental low power implementation techniques like clock gating and power gating.

- Memory Familiarity : Familiarity with various memory types and their usage in design (SRAM, DRAM, Register File (RF), Flop-based FIFOs).

- Communication : Good written and verbal communication skills are required.

Preferred Qualifications :

- Front-to-Back Flow Experience : Experience with synthesis (synth) and Place and Route (PnR) flows.

- Advanced Nodes : Understanding of power and performance implications specific to the latest technology nodes.

- RTL Power Optimization : Experience with RTL power optimization using specialized tools such as Power-Artist.

- Tooling : Proficiency with version control systems and familiarity with library characterization tools and analysis.

- Design Profiling : Experience with FSDB (Fast Signal Database) analysis for detailed design profiling