We are looking for a skilled Physical Verification (PV) Engineer with 3+ years of hands-on experience in full-chip and block-level verification. The ideal candidate should have strong expertise in DRC, LVS, and sign-off methodologies across advanced technology nodes.

Key Responsibilities :

- Perform DRC, LVS, ERC, and Antenna checks for block and full-chip level designs

- Debug and resolve physical verification violations with design/layout teams

- Work on sign-off verification flows for advanced nodes (7nm/5nm/FinFET is a plus)

- Run and analyze LVS comparison, shorts/opens debugging

- Collaborate with PD (Physical Design) and layout teams for closure

- Handle PEX (Parasitic Extraction) and support timing/power teams

- Develop and maintain runsets, scripts, and automation flows

Required Skills :

Strong hands-on experience in :

- DRC / LVS / ERC / PEX

- Layout debugging and verification closure

Good understanding of :

- Semiconductor fundamentals & VLSI design flow

- Design rules and foundry decks

Experience with tools :

- Calibre (Mentor Graphics)

- IC Validator (Synopsys) (added advantage)

Scripting knowledge :

- TCL / Perl / Python (preferred)

Preferred Qualifications :

- Experience in advanced nodes (16nm and below)

- Exposure to full-chip verification flows

- Good problem-solving and debugging skills

- Strong communication and teamwork abilities