Physical Design Lead

Role : Physical Design Lead

Experience : 812 Years

We are looking for an experienced Physical Design Lead to drive end-to-end chip implementation and signoff activities for advanced technology nodes.

Key Responsibilities :

- Lead end-to-end Physical Design (PD) flow from Netlist to GDSII

- Own floorplanning, placement, CTS, routing, and signoff closure

- Drive timing closure (STA) and physical verification signoff

- Ensure PPA (Power, Performance, Area) optimization at block and chip level

- Collaborate with RTL, DFT, and Verification teams for design convergence

- Debug and resolve timing, congestion, and design rule violations

- Manage multi-block integration and hierarchical design flows

- Ensure clean tape-out delivery within schedule

Technical Skills Required :

- Strong experience in 16nm / 7nm technology nodes

- Hands-on expertise in :

1. Floorplanning

2. Clock Tree Synthesis (CTS)

3. Static Timing Analysis (STA)

4. Physical Verification

- Expertise in industry-standard tools :

1. ICC2

2. Innovus

3. Calibre

4. Formality

5. LEC (Logical Equivalence Checking)

Additional Skills :

- Strong understanding of timing closure methodologies

- Knowledge of power optimization techniques

- Experience in multi-voltage and low-power designs

- Exposure to signoff flows and tape-out process

- Understanding of block-level and full-chip integration

Leadership Requirements :

- Ability to mentor engineers and drive execution

- Strong coordination with cross-functional teams (RTL, DFT, Verification, STA)

- Ownership of project delivery and signoff commitments