Physical Design Engineer

Role : Physical design engineer

Location : Pune / Hyderabad

Experience : 4+ Years

Industry : Semiconductor / VLSI

Job Summary :

The ideal candidate will have hands-on experience in Place & Route (P&R), timing closure, and DRC closure, along with a deep understanding of advanced semiconductor nodes. This role requires end-to-end ownership of physical design blocks, ensuring high-quality deliverables aligned with project timelines and signoff requirements.

Key Responsibilities :

Physical Design & Implementation :

1. Floorplanning

2. Placement

3. Clock Tree Synthesis (CTS)

4. Routing and optimization

- Drive Place & Route (P&R) using industry-standard tools like Cadence Innovus

- Ensure optimal Power, Performance, and Area (PPA) during implementation

Static Timing Analysis (STA) :

- Analyze and resolve :

1. Setup and hold violations

2. Timing derates and uncertainties

3. Clock domain crossings (CDC) (if applicable)

- Drive timing closure at subchip level with strong debugging and optimization techniques

- Collaborate with design teams to fix timing issues through ECO implementations

Physical Verification (PV) & Signoff :

- Work on Physical Verification checks including :

1. DRC (Design Rule Check)

2. LVS (Layout vs Schematic) (if applicable)

3. Antenna, EM, IR drop analysis

- Ensure clean signoff deliverables as per foundry requirements

Integration & Collaboration :

1. Front-end design teams (RTL/Logic)

2. Integration teams

3. Signoff and verification teams

- Resolve timing, congestion, and physical design issues during integration

- Participate in design reviews and technical discussions

Ownership & Delivery :

- Independently own assigned subchips/blocks from P&R to signoff

- Track progress and ensure milestone-based delivery

- Maintain high quality and accuracy in all deliverables

- Proactively identify risks and drive timely resolution

Required Skills & Experience :

Core Technical Skills :

- Expertise in Static Timing Analysis (STA) and timing closure

- Proven experience in DRC closure and Physical Verification

- Hands-on experience with :

1. Cadence Innovus (P&R)

2. Synopsys PrimeTime (STA)

Physical Design Expertise :

- Clock Tree Synthesis (CTS) and timing optimization

- Routing, extraction, and post-route optimization

- ECO flow and implementation

Analysis & Debugging :

1. Timing violations (setup/hold)

2. Congestion and density issues

3. DRC and signoff violations

- Experience in handling advanced nodes (e.g., 5nm, 7nm, 3nm) is a plus

Additional Skills :