Physical/Backend Engineer - VLSI/RTL

About the Role :

We are looking for a highly skilled and detail-oriented Physical / Backend Engineer to join our VLSI engineering team. The ideal candidate should have strong hands-on experience in physical design, timing closure, and RTL-to-GDSII flow execution for advanced nodes. You will be responsible for delivering high-quality SoC designs on cutting-edge technology nodes (5nm and below), ensuring optimized performance, power, and area targets.

Key Responsibilities :

- Own and enhance complete physical design flows from RTL to GDSII.

- Collaborate closely with RTL, DFT, and verification teams for smooth integration and sign-off.

- Drive optimization of design metrics including timing, power, area, and congestion through continuous flow tuning.

- Develop, refine, and maintain physical design methodologies and best practices.

- Ensure successful timing closure and tape-out across advanced SoC programs.

Required Qualifications :

- 5+ years of experience in physical design / backend implementation of SoCs.

- Strong understanding of digital design principles, timing analysis, and physical design constraints.

- Hands-on experience with EDA tools for Place & Route (P&R), Static Timing Analysis (STA), and physical verification.

- Strong scripting capabilities in Python, Tcl, and Shell for automation and flow enhancements.

- Bachelors / Masters degree in Engineering exclusively from IIT / NIT / BITS.

Preferred Qualifications :

- Experience working on advanced process nodes such as 7nm, 5nm, or 3nm.

- Familiarity with IP integration, hierarchical design, and chip-level assembly.

- Knowledge of version control systems (Git) and CI/CD workflows.

- Exposure to ML or data-driven methodologies for design optimization.

Soft Skills :

- Strong analytical and structured problem-solving abilities.

- Excellent communication and collaboration skills.

- Ability to thrive in a fast-paced, high-ownership, and deadline-driven environment.