Role Overview :

We are seeking a highly skilled SoC Design Verification Engineer to join our semiconductor engineering team. The ideal candidate will be responsible for architecting, developing, and executing comprehensive verification environments for complex SoCs containing embedded processors, high-speed interfaces, and mixed-signal components.

The role requires strong expertise in SystemVerilog, UVM, constrained random verification methodologies, and functional coverage-driven verification.

Key Responsibilities :

Verification Architecture & Development :

- Architect and develop block-level and full-chip verification environments.

Create scalable verification frameworks using :

1. SystemVerilog

2. UVM (Universal Verification Methodology)

3. Constrained Random Verification

- Develop reusable verification components and testbenches.

- Define verification strategies and methodologies for complex SoCs.

Test Planning & Coverage :

- Derive verification plans from design specifications.

- Define functional and code coverage metrics.

- Develop and execute :

1. SystemVerilog Tests

2. UVM Test Cases

3. C-Based Tests

- Drive coverage closure and verification signoff.

Debug & Validation :

- Debug RTL and Gate-Level simulation failures.

- Collaborate closely with design teams to identify and resolve functional issues.

- Validate fixes and verify design changes.

- Investigate and reproduce silicon bugs in simulation environments.

FPGA & Silicon Validation :

- Develop diagnostics for FPGA-based pre-silicon validation.

- Support ASIC validation and post-silicon verification activities.

- Validate software workarounds and hardware fixes.

Test & Manufacturing Support :

- Convert verification test cases into production test patterns.

- Support ATE (Automated Test Equipment) vector bring-up and validation.

- Collaborate with Product and Test Engineering teams.

Automation & Methodology Enhancement :

- Evaluate and adopt advanced verification methodologies.

- Develop automation scripts to improve verification efficiency.

- Enhance regression, reporting, and coverage analysis flows.

Required Skills & Experience :

- 4+ years of experience in SoC Design Verification.

- Strong expertise in :

1. SystemVerilog

2. UVM

3. SVA (SystemVerilog Assertions)

4. Constrained Random Verification

- Experience verifying :

1. Complex SoCs

2. Embedded CPU-based Designs

3. High-Speed Interfaces

4. Mixed-Signal Subsystems

- Strong debugging skills for RTL and Gate-Level simulations.

- Experience in test planning, coverage analysis, and coverage closure.

- Knowledge of ASIC and FPGA validation methodologies.

Preferred Skills :

- Experience with embedded software-driven verification.

- Knowledge of industry-standard simulators and EDA tools.

- Exposure to formal verification methodologies.

- Experience with scripting languages such as :

1. Python

2. Perl

3. Shell Scripting

- Familiarity with ATE validation and manufacturing test flows.

Education :

- B.Tech / M.Tech in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related disciplines.

Preferred Candidate Profile :

- Strong analytical and debugging skills.

- Excellent understanding of semiconductor verification methodologies.

- Ability to work effectively with cross-functional design, validation, and test teams.

- Strong communication and collaboration skills.

- Passion for delivering high-quality silicon products.