Mirafra Technologies - Senior Physical Design Engineer

Job Title : Sr. Physical Design Engineer

Company : Mirafra Software Technologies Pvt Ltd

Location : Others/Bengaluru, Karnataka, India

Experience : 3-8 Years

Job Description :

Mirafra Software Technologies is seeking a highly motivated and experienced Sr. Physical Design Engineer to join our growing team in Bengaluru. As a Sr. Physical Design Engineer, you will be responsible for various aspects of physical design implementation, from floorplanning to tape-out, for complex SoCs. You will work closely with RTL designers, circuit designers, and other physical design engineers to ensure successful execution of projects.

Responsibilities :

- Participate in all aspects of physical design implementation including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, power integrity analysis, and physical verification.

- Develop and maintain physical design methodologies and flows.

- Perform timing analysis and closure using industry-standard tools (e.g., PrimeTime, Tempus).

- Perform power analysis and optimization using industry-standard tools (e.g., RedHawk, Voltus).

- Work closely with RTL designers to resolve timing and power issues.

- Work with circuit designers to optimize layout for performance and power.

- Perform physical verification checks (DRC, LVS, ERC) and resolve violations.

- Generate and review all required physical design documentation.

- Mentor junior engineers and provide technical guidance.

- Participate in tape-out activities.

- Contribute to continuous improvement of physical design processes and methodologies.

- Debug and resolve complex physical design issues.

- 3-8 years of experience in physical design implementation.

- Strong understanding of CMOS technology and deep sub-micron design rules.

- Proficiency in using industry-standard physical design tools such as Synopsys ICC/Innovus, Cadence Encounter, and Mentor Graphics Calibre.

- Experience with floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, power integrity analysis, and physical verification.

- Strong timing analysis and closure skills.

- Experience with scripting languages such as TCL and Perl.

- Excellent problem-solving and analytical skills.

- Strong communication and interpersonal skills.

- Ability to work independently and as part of a team.

- Experience with low power design techniques is a plus.

- Experience with advanced process nodes (e.g., 7nm, 5nm) is a plus.