Mirafra Technologies - Formal Verification Engineer

Job Description :

Key Responsibilities :

- Develop and execute formal verification plans for IPs/SoCs

- Write formal properties, assertions, and constraints using SystemVerilog Assertions (SVA)

- Perform property checking, equivalence checking, and coverage analysis

- Debug design and verification issues using formal tools

- Collaborate closely with RTL designers and DV teams to close verification gaps

- Analyze counterexamples and root cause design failures

- Ensure completeness of formal verification coverage

Required Skills :

- Strong understanding of digital design concepts (RTL, FSMs, protocols)

- Hands-on experience with formal verification methodologies

- Expertise in SystemVerilog and SVA (SystemVerilog Assertions)

- Experience with industry tools like JasperGold, VC Formal, or Questa Formal

- Good debugging and problem-solving skills

- Familiarity with protocols like AXI, AHB, APB is a plus

Preferred Qualifications :

- Experience in equivalence checking (LEC)

- Knowledge of low-power verification and CDC/RDC concepts

- Exposure to scripting languages like Python, Perl, or Tcl

- Prior experience in SoC/IP level verification

Education :

B.Tech / M.Tech in Electronics, Electrical, or related field