Description :

Location : Bangalore

Experience : 3+ Years

Job Description :

- Responsible for custom layout design of memory blocks (SRAM, DRAM, ROM, Register Files, etc.)

- Perform DRC/LVS checks, parasitic extraction, and layout optimization

- Collaborate closely with circuit design teams to ensure performance, area, and reliability targets are met

- Hands-on experience in Cadence Virtuoso, Calibre/Assura, and deep submicron/FinFET technologies preferred (2nm to 7nm TSMC)

Key Responsibilities :

- Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.).

- Work on floorplanning, transistor-level layout, device matching, and parasitic optimization.

- Ensure DRC/LVS clean layouts with adherence to foundry design rules.

- Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area).

- Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts.

- Deliver high-quality layouts meeting project deadlines and silicon success.

Required Skills :

- Strong expertise in memory layout (SRAM, ROM, CAM, Register Files).

- Hands-on experience with Cadence Virtuoso, Mentor Calibre, Synopsys tools.

- Deep knowledge of foundry design rules (DRC, LVS, ERC, ANT, etc.).

- Familiarity with advanced process nodes (7nm/5nm/3nm preferred).

- Strong understanding of layout-dependent effects (LDE), electromigration, IR drop.

- Good communication and ability to work in cross-functional teams.