MediaTek - STA Engineer

Job Description :

Key Responsibilities :

- Perform pre-route timing checks and QoR cleanup to eliminate SDC issues, ensuring quality handoff for STA.

- Ensure timing correlation between PnR and STA and provide timely feedback to the Physical Design (PD) team.

- Generate block-level HS sessions and use top context from SoC for Block-SoC interface timing closure.

- Generate timing ECOs using Tweaker/PrimeClosure.

- Analyze timing reports and identify both design-related and constraint-related issues.

Technical Skills :

- Timing Closure : Hands-on experience with high-frequency blocks (>GHz range).

- EDA Tools : Experience with Primetime, Tweaker/PrimeClosure, Innovus.

- DFT Awareness : Strong understanding of DFT mode requirements for timing signoff.

- Physical Design Knowledge : Good understanding of physical design flow, ECO implementation, and multi voltage domain considerations.

- Timing Analysis : Strong knowledge of SDC constraints, OCV, AOCV, and POCV analysis.

- Programming/Scripting : Strong TCL and scripting skills (Python/Perl/Shell a plus).

- Problem-Solving : Ability to identify timing issues and propose practical solutions collaboratively.

Experience :