Description :

We are looking for an experienced Low Power Design Verification Engineer with strong hands-on expertise in low power verification at both IP and SoC levels.

The ideal candidate should have solid exposure to UPF-based low power flows, GLS, and C-based SoC verification.

Key Responsibilities :

- Perform Design Verification (DV) for complex IPs and SoCs using SystemVerilog and UVM

- Develop and execute verification test plans, environments, sequences, checkers, and coverage

- Implement and verify low power intent using UPF

- Validate power scenarios including power gating, isolation, retention, and level shifters

- Execute and debug Low Power Gate Level Simulations (GLS)

- Work on IP-level and SoC-level verification, including integration testing

- Develop and run C/C++ based SoC verification tests

- Analyze failures, debug issues, and collaborate closely with design and architecture teams

- Ensure functional, code, and power coverage closure

Required Skills & Experience :

- 6 to 8+ years of strong experience in Design Verification

- Hands-on experience with Low Power Verification using UPF (Mandatory)

- Proven experience at both IP and SoC verification levels

- Strong experience in Low Power GLS (Mandatory)

- Experience with C-based SoC verification (Mandatory)

- Proficiency in SystemVerilog, UVM

- Familiarity with power-aware simulation flows and EDA tools

- Strong debugging, problem-solving, and communication skills

Preferred Skills (Good to Have) :

- Experience with advanced power management flows

- Exposure to post-silicon validation

- Experience in working with multi-power domain SoCs