Leadsoc Technologies - FPGA/Silicon Validation Engineer

About the Role :

Own integration and bring-up across FPGA and silicon EVBs for high-speed interfaces (PCIe/Ethernet/DDR4/DDR5). The role is ~80% system/integration & validation, ~20% RTL design, with board work biased ~80% debug / 20% simple design.

Key Responsibilities

- FPGA Design Flow & Validation : Synthesis, P&R, timing closure (Vivado/Quartus); constraints (XDC/SDC); image generation and lab bring-up.

- RTL (20%) : Targeted Verilog/SystemVerilog changes, glue logic, wrappers, and design-for-debug hooks.

- Interface Bring-up : PCIe, Ethernet, DDR4/5 & memory subsystemslink training, calibration, throughput/latency and margining.

- System-level Testing : Develop/execute test plans; corner, stress, and interoperability tests; performance and power characterization.

- Post-Silicon Validation : EVB setup, firmware/driver coordination, silicon feature enablement, errata reproduction and workarounds.

- Debugging : Board-level (oscilloscope, LA, protocol analyzers, JTAG) and design-level (waveforms, assertions, CDC/timing).

- Documentation & Reporting : Clear logs, defect reports, and release/readiness summaries; collaborate with procurement/installation for test assets.

Requirements :

- Strong RTL design/implementation (Verilog/SystemVerilog), hands-on FPGA flow and validation.

- Experience in system-level testing and post-silicon validation/bring-up.

- Proven debug skills at board and design levels; comfort with lab instruments and protocol analyzers.

- Familiarity with Xilinx (Vivado) and/or Intel (Quartus) toolchains.

- Working knowledge of PCIe, Ethernet, DDR4/5, memory protocols/subsystems.

- Scripting for productivity (TCL/Python/Bash); version control (Git).

- B.E./B.Tech/M.E./M.Tech in ECE/EE/CS or equivalent.

Nice to Have :

- Linux host tools, basic driver/firmware interaction for bring-up.

- CDC analysis, STA, SVAs; emulation/prototyping (HAPS/Protium) exposure.

- CI (Jenkins/GitLab), Jira, test automation dashboards.

30:60:90 Day Outcomes :

- 30d : FPGA sandbox up; first interface link-up with baseline measurements.

- 60d : Stable automated test runs; defects triaged with root-cause hypotheses.

- 90d : Multi-interface validation coverage; performance/power reports and sign-off criteria in place.

Interview Process :

1) Technical screen (RTL/FPGA/protocols)

2) System & lab debug deep-dive

3) Practical/log-based exercise

4) Managerial fit.