Leadsoc Technologies - DFT Lead

Job Title : DFT Lead

Location : Bangalore Urban, Karnataka, India

Job Description :

Leadsoc Technologies is seeking a highly motivated and experienced DFT (Design for Test) Lead to join our growing engineering team. As a DFT Lead, you will be responsible for leading and executing DFT activities for complex SoCs, ensuring high test coverage and manufacturability. You will work closely with design, verification, and physical design teams to implement DFT strategies and methodologies.

Responsibilities :

- DFT Strategy and Planning : Develop and implement comprehensive DFT strategies for complex SoCs, considering test coverage, area overhead, and power consumption.

- DFT Architecture : Define and implement DFT architectures, including scan insertion, ATPG, memory BIST, logic BIST, and boundary scan.

- Memory BIST and Logic BIST : Implement and verify memory BIST and logic BIST solutions.

- DFT Verification : Develop and execute DFT verification plans to ensure the correctness and effectiveness of DFT implementations.

- Tool Expertise : Proficiently use industry-standard DFT tools from vendors like Synopsys, Cadence, and Mentor Graphics.

- Mentoring : Mentor and guide junior DFT engineers.

- Test Pattern Validation : Work with ATE engineers to validate test patterns on silicon.

- Failure Analysis : Assist in failure analysis and debug of silicon failures.

Technical Skills :

- Experience with scan insertion, ATPG, memory BIST, logic BIST, and boundary scan.

- Proficiency in using industry-standard DFT tools (e.g., Synopsys TetraMAX, Cadence Encounter Test, Mentor Graphics Tessent).

- Experience with scripting languages (e.g., Perl, Python, TCL).

- Knowledge of semiconductor manufacturing processes and testing techniques.

Soft Skills :

- Strong problem-solving and analytical skills.

- Ability to work independently and as part of a team.

- Ability to manage multiple tasks and prioritize effectively.