Lead FPGA Design Engineer - System Verilog

Description :

- Position : Lead FPGA Design Engineer

- Experience : 8yr

- Location : Bangalore

- Skill Set : FPGA Design, RTL design, digital design,FPGA development, skilled in SystemVerilog/Verilog, AXI4 protocols,and Xilinx Vivado, with strong expertise in DSP and OFDM-based baseband processing.

- Working Days : 5

Key Responsibilities :

- Lead RTL architecture definition, specification, and design for complex communication systems.

- Mentor and guide engineers in RTL design, verification, and FPGA implementation using SystemVerilog.

- Perform synthesis, FPGA implementation, and timing closure.

- Collaborate with hardware/software teams to troubleshoot and optimize system performance.

- Ensure compliance with design methodologies and best practices.

Required Skills :

- 8+ years of experience in RTL design, verification, and FPGA development.

- Expertise in digital design principles and FPGA workflows.

- Proficiency in SystemVerilog/Verilog and AXI4 (AXI4, AXI4-Lite, AXI4-Stream) protocols.

- Strong hands-on experience with Xilinx FPGAs and Vivado tools.

- Knowledge of DSP concepts (FFT, linear/complex algebra).

- Experience in baseband processing for wireless systems (OFDM).

- Proven leadership, innovation, and cross-functional collaboration skills.