Lead DFT Engineer - ATPG/MBIST

Position Overview :

We are looking for an experienced Senior DFT Engineer with strong expertise in Scan, ATPG, MBIST, LBIST, and JTAG/TAP validation. The candidate will own the full DFT implementation flow from DFT architecture definition to pattern generation, validation, and sign off ensuring high test coverage, robust quality, and seamless integration into SoC and post-silicon test environments.

Key Responsibilities :

DFT Architecture & Planning :

- Define and implement DFT architecture for complex SoCs and IPs covering scan, MBIST, LBIST, and boundary scan (IEEE 1149.x).

- Develop DFT specifications aligned with SoC requirements, test coverage goals, and manufacturing test constraints.

- Drive clock/reset/power domain-based DFT partitioning, test mode planning, and integration with SoC design flow.

Scan & ATPG Implementation

- Perform scan insertion and test point insertion at block and SoC level using industry-standard tools.

Required Skills & Experience :

- Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering.

- 8 to 15 years of hands-on experience in DFT architecture, implementation, and validation.

- Strong knowledge of scan-based DFT, ATPG, MBIST, LBIST, and boundary scan concepts.

- Hands-on experience with one or more of the following tools:

Synopsys : DFT Compiler, TetraMAX, TestMAX

Cadence : Modus, Encounter Test

Mentor/Siemens : Tessent suite (Scan, ATPG, MBIST, LBIST)

- Experience in gate-level simulations (GLS), waveform debug, and pattern validation.

- Deep understanding of fault models, coverage metrics, and design-for-test sign-off methodologies.