Halma India - Design Verification Engineer - UVM/System Verilog

Job Description :

Key Responsibilities :

- Develop verification plans, environments, and testbenches using SystemVerilog and UVM

- Perform functional verification and ensure robust coverage metrics

- Debug and resolve verification issues efficiently

- Collaborate with design teams for seamless integration and verification closure

Required Skills :

- Strong experience in Fabric/NOC/Interconnect block verification

- Knowledge of AMBA suite protocols (AXI/ACE), PCIe, CXL, interrupt handling, and power management

Good to Have :

Who Were Looking For :

- Excellent communication and teamwork abilities

- Ability to work independently and deliver high-quality verification