Description :

Our client is looking for a PCIe Verification Engineer to join their Team DIRECTLY

Skills required :

- Strong hands-on experience with Avery PCIe VIP (integration, debug, customization).

- In-depth knowledge of PCIe protocol (Gen4/Gen5 or higher).

- Solid experience in System Verilog / UVM methodology.

- Strong debug and problem-solving skills using simulators like Questa, VCS, or Xcelium.

- Familiarity with coverage-driven verification and constraint random testing.

- Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell).

- Excellent communication skills and ability to work independently in a fast-paced environment.

Responsibilities :

- Perform functional and compliance verification of PCIe-based SystemC IPs and subsystems.

- Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol-level verification.

- Debug complex issues across transaction, data link, and physical layers of PCIe.

- Analyze and interpret PCIe specifications for test planning and coverage.

- Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance.

- Generate and review verification plans, test reports, and coverage metrics.

Preferable

B.E/M. E/MTech or B.S/MS in Electronics or Computer Engineering