Key skills and qualifications

- 5+ years of FPGA design and development experience.

- Strong in any high-speed serial protocols (PCIe, NVMe, CXL preferred)

- Proven skills in high-speed FPGA design, including CDC handling, timing closure, and interface validation.

- Hands-on experience with FPGA synthesis/implementation tools (Xilinx Vivado: synthesis, place-and-route, timing closure, on-board debug).

- Experience with FPGA simulation tools (ModelSim, Questa, VCS, or Vivado Simulator) for design validation.

Responsibilities :

- Design, develop, and maintain FPGA-based solutions for high-performance systems

- Implement and validate high-speed serial interfaces such as PCIe, NVMe, and/or CXL

- Perform FPGA synthesis, place-and-route, and timing closure using Xilinx Vivado

- Address complex timing challenges, including clock domain crossing (CDC) and high-speed timing constraints

- Perform on-board debug and interface validation using integrated logic analyzers and lab tools

- Develop and execute simulation testbenches for functional and timing verification