We are seeking a highly skilled Formal Verification Engineer with strong hands-on experience in Cadence JasperGold to join our verification team. The role requires deep expertise in formal methodologies, assertion-based verification, and advanced debug techniques to ensure correctness, robustness, and quality of complex SoC and IP designs.

The ideal candidate should be capable of owning formal verification tasks end-to-end and actively collaborating with design, simulation, and architecture teams.

Key Responsibilities :

- Lead and execute formal verification of complex RTL designs using Cadence JasperGold

- Develop and maintain SystemVerilog Assertions (SVA) to validate functional correctness and design intent

- Apply formal verification methodologies including :

1. Block-level and IP-level formal verification

2. Property checking and proof convergence

3. Equivalence checking and protocol verification

- Analyze, debug, and resolve failing properties, including deep analysis using trace, trigger, and counterexample debugging

- Work closely with RTL designers to improve design quality and verifiability

- Complement formal verification with simulation-based verification using UVM, where necessary

- Develop reusable formal verification frameworks, constraints, and checkers

- Actively review designs for formal friendliness and help close verification gaps early in the design cycle

- Document verification strategies, results, and coverage metrics

Required Skills & Experience :

- 5+ years of hands-on experience in Formal Verification

- Expert-level experience with Cadence JasperGold (mandatory)

- Strong proficiency in SystemVerilog, including SystemVerilog Assertions (SVA)

- Solid experience with UVM-based verification environments

- Strong debug skills with expertise in :

1. Formal counterexample analysis

2. Trace-based debug

3. Trigger-based debug techniques

- Ability to independently own verification challenges and drive them to closure

- Deep understanding of digital design concepts, RTL coding styles, and verification best practices

Preferred / Nice-to-Have Skills :

- Experience with SoC-level formal verification

- Familiarity with protocol verification (AMBA, AXI, APB, etc.)

- Knowledge of low-power verification concepts

- Exposure to equivalence checking and CDC/RDC formal checks

- Experience working in fast-paced product development environments

Location : Bangalore