Job Title : Electronic Design Automation Engineer

Experience : 5 - 8 yrs

Location : Hyderabad

Job Summary :

We are seeking an experienced Senior Chip Design Engineer with deep expertise in one or more of the following domains : Power Optimization, Timing Optimization, and Functional Safety Analysis. The ideal candidate will have hands-on experience with industry-standard EDA tools, strong RTL-to-GDSII understanding, and solid scripting capabilities to automate design flows.

Must Have :

- Chip design

- RTL Design

Key Responsibilities :

- Apply low-power design techniques and methodologies, including the use of Unified Power Format (UPF).

- Conduct Static Timing Analysis (STA) and manage timing closure using Synopsys Design Constraints (SDC).

- Perform Functional Safety Analysis aligned with ISO 26262, including techniques such as FMEDA and Fault Tree Analysis (FTA).

- Work with EDA tools from leading vendors such as Synopsys, Cadence, and Siemens EDA.

- Develop and maintain RTL using Verilog/SystemVerilog.

- Create automation scripts using Python and Tcl for tool flow development and optimization.

- Contribute to all phases of the chip design flow, from RTL to GDSII.

- Collaborate with cross-functional teams to debug, analyze, and solve complex design and timing issues.

- Communicate technical concepts clearly to both technical and non-technical stakeholders.

Required Qualifications :

- Bachelor's or Masters degree in Electrical Engineering, Computer Engineering, or a related field.

- 5+ years of hands-on experience in chip design, with a strong emphasis on RTL design, synthesis, STA, or power integrity.

- Proficiency in hardware description languages (HDLs) Verilog, SystemVerilog.

- Strong knowledge of EDA tools (Synopsys, Cadence, Siemens).

- Solid scripting experience using Python and Tcl.