DV Lead/Manager

Job Summary :

We are seeking an experienced Design Verification Lead with strong expertise in PCIe (Peripheral Component Interconnect Express) and NVMe (Non-Volatile Memory Express) protocols. The ideal candidate will lead verification efforts for high-performance SoC or IP designs, drive verification strategy, and ensure robust coverage and quality sign-off.

Key Responsibilities :

- Lead end-to-end verification planning, environment development, and test execution for PCIe/NVMe-based subsystems or IPs.

- Define verification architecture, methodologies, and reusable testbench components using UVM/SystemVerilog.

- Develop, review, and maintain test plans aligned with design specifications and functional requirements.

- Drive constrained-random, directed, and coverage-driven verification approaches.

- Integrate and verify third-party IPs, focusing on protocol compliance (PCIe Gen3/Gen4/Gen5, NVMe 1.3/1.4).

- Perform debug, root-cause analysis, and work closely with design, validation, and architecture teams.

- Ensure functional and code coverage closure and support regression automation.

- Mentor and guide junior verification engineers.

- Collaborate with software, firmware, and validation teams for system-level verification and interoperability testing.