Digital Verification Engineer

Description :

DV Engineer (SystemVerilog/UVM) - UFS Protocol

Role Overview :

The DV Engineer (SystemVerilog/UVM) is a highly specialized role requiring a minimum of 5+ years of experience in semiconductor design verification.

This position offers flexible location options (India - Remote / Hybrid / On-site) and is designated for a Long-term semiconductor project with an Immediate Start Date.

The incumbent will apply strong hands-on expertise in SystemVerilog (SV) and UVM to deliver comprehensive verification for complex designs, specifically focusing on UFS protocol validation.

Job Summary

We are seeking an experienced Design Verification Engineer (5+ years) with deep, hands-on expertise in SystemVerilog and the Universal Verification Methodology (UVM). The ideal candidate must possess a solid understanding of UFS protocols (UFS3 / UFS4 / UFS5) and proven experience in developing complete testbenches, executing test plans, and achieving functional and code coverage closure. This role requires strong independent debugging skills and the ability to contribute immediately to a long-term, high-impact semiconductor project.

Key Responsibilities and Verification Deliverables

Verification Environment Development :

- Demonstrate Strong hands-on experience in SystemVerilog (SV) and UVM to lead the design and implementation of efficient and reusable verification environments (testbenches).

- Expertise in testbench development, including implementing BFMs (Bus Functional Models), monitors, scoreboards, and sequence hierarchies.

Test Plan and Execution :

- Develop detailed, comprehensive test plans based on design specifications and protocol requirements.

- Drive testcase creation (constrained-random and directed) to ensure complete functional coverage and corner-case validation.

Protocol Expertise :

- Apply Solid understanding of UFS protocols (UFS3 / UFS4 / UFS5) to implement accurate protocol checkers, coverage groups, and scenario generation.

- Simulate and verify compliance with the latest UFS specifications, ensuring robust performance and interoperability.

Debugging and Closure :

- Utilize Experience in debugging complex verification failures at the RTL and system level, tracing issues through waveforms and log files.

- Manage and track coverage metrics (functional and code coverage) and drive methodologies for achieving closure and quality sign-off.

Collaboration and Independence :

- Possess the Ability to work independently on complex verification blocks and collaborate effectively with cross-functional teams (Design, Software, Architecture).

Mandatory Skills & Qualifications :

Experience : Minimum 5+ years in Design Verification.

Methodology : Strong hands-on experience in SystemVerilog (SV) and UVM.

Protocol : Solid understanding of UFS protocols (UFS3 / UFS4 / UFS5).

Process : Expertise in testbench development, test plans, and testcase creation.

Closure : Experience in debugging, coverage, and verification methodologies.

Preferred Skills

- Knowledge of scripting languages (Python/Perl) for automation and flow enhancement.

- Familiarity with advanced verification techniques (Formal Verification, Emulation).

- Experience with protocols complementary to UFS (e.g., PCIe, AMBA AXI/AHB).