DFT Senior Engineer - RTL Design

Responsibilities:

- Minimum 5 years of industry experience

- Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification (Mentor DFT Tools, Synopsys Simulation Tools)

- Experience with RTL design and Design verification principles

- Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure

- Experience with industry standard simulation tools, including Verilog, and scripting languages like Perl, Python, Shell or Tcl

- Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)

- Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

- Work independently to generate test plans, run simulations and debug failures on RTL and Gate Level

- Strong fundamental knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL)

- Direct experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues

- Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD

- Experience with STA constraints development and analysis for DFT modes and SDF simulations

- Ability to communicate and work with multi-disciplined teams across multiple sites and time time zones.