We are looking for an experienced DFT Lead to drive end-to-end Design for Test strategy, implementation, and signoff for complex ASIC/SoC designs while leading a high-performing team.

Key Responsibilities :

- Own and define end-to-end DFT strategy and architecture for ASIC/SoC projects

- Drive complete DFT implementation from RTL to signoff

- Lead activities like :

1. Scan insertion and scan architecture planning

2. BIST / MBIST implementation

3. ATPG pattern generation and fault coverage closure

4. Pattern validation (with and without timing)

- Ensure high fault coverage and test quality targets are met

- Perform DFT signoff readiness and closure activities

- Identify and resolve DFT-related design and implementation issues

- Work on DFT timing analysis and constraints coordination with STA teams

- Optimize test cost, test time, and coverage efficiency

- Drive continuous improvement in DFT methodology and flows

Technical Skills Required :

- Strong hands-on experience in :

1. Scan insertion and compression techniques

2. BIST (Logic BIST)

3. MBIST (Memory BIST)

4. ATPG and fault coverage analysis

5. Pattern generation and validation

- Strong understanding of DFT architecture and SoC integration

- Experience in DFT signoff flows

- Knowledge of fault models (stuck-at, transition, bridging faults)

- Exposure to DFT timing analysis and constraints handling

Additional Skills :

- Strong understanding of SoC design and verification flow

- Knowledge of test compression and coverage improvement techniques

- Experience in debugging scan chain and MBIST issues

- Understanding of silicon bring-up and post-silicon validation (preferred)

Leadership Requirements :

- Proven experience in leading DFT teams

- Ability to mentor engineers and drive technical execution

- Strong coordination with:

1. RTL Design teams

2. Verification teams

3. Physical Design & STA teams

4. Test engineering teams

- Ownership of project delivery and milestone tracking

Role Summary:

DFT Lead responsible for end-to-end test strategy, implementation, and signoff of scan, BIST, MBIST, and ATPG flows while leading a team and ensuring high-quality, testable ASIC/SoC delivery.