Description :

Digital Design for Test (DFT) Engineer

We are seeking a highly skilled and experienced Digital Design for Test (DFT) Engineer to join our team. The successful candidate will be a key contributor to the design, implementation, and verification of Design for Test (DFT) structures for complex Application-Specific Integrated Circuits (ASICs) and Systems-on-Chip (SoCs).

Key Responsibilities :

- DFT Architecture and Implementation : Define, implement, and verify DFT structures, including SCAN, MBIST (Memory Built-In Self-Test), and JTAG/iJTAG (IEEE 1149.1/1687) architectures.

- Test Pattern Generation : Develop and validate high-quality ATPG (Automatic Test Pattern Generation) vectors for various fault models (e.g., stuck-at, transition, bridging faults) to achieve high test coverage.

- DFT Tool Flow Development : Design, implement, and maintain efficient DFT and test generation flows using industry-standard tools, with a strong preference for Mentor Graphics Tessent tools.

- Scripting and Automation : Develop and utilize advanced scripting/programming skills (e.g., Python, Perl, TCL) to automate DFT design, verification, and debug processes.

- DFT Sign-off : Collaborate with verification and physical design teams to ensure DFT implementation meets all performance, power, area, and timing requirements for tape-out.

- Silicon Bring-up and Debug : Actively participate in post-silicon validation, test vector deployment on Automated Test Equipment (ATE), and debug of DFT-related issues on silicon.

- Documentation and Review : Generate detailed documentation for the DFT methodology, design, and test patterns, and participate in design reviews.

Required Qualifications :

- Education : Bachelor's degree (B.Tech) in Electrical Engineering, Electronics Engineering, or a related field.

- Experience : 4+ years of hands-on experience in DFT implementation, verification, and silicon bring-up.

- DFT Expertise : In-depth, practical experience with DFT methodologies, including SCAN insertion, MBIST generation, and ATPG for complex digital designs.

- Tool Proficiency : Proven expertise in ASIC DFT design and ATPG/SCAN tools, with Mentor Graphics Tessent being highly preferred.

- Protocol Knowledge : Strong understanding of JTAG/iJTAG protocols and architectures and their implementation in SoCs.

- Programming Skills : Excellent scripting and programming skills for developing automation flows and utility tools (e.g., Perl, Python, TCL).

- Fault Modeling : Solid knowledge of various fault modelling techniques and their impact on test coverage and quality.

- Product Life Cycle : Familiarity with the overall SoC design cycles, from specification to silicon bring-up and mass production.

Desired Attributes :

- Proactive Ownership : Quick learner, proactive, self-motivated, with a strong sense of ownership and responsibility for assigned tasks.

- Problem-Solving : Excellent analytical and problem-solving skills for complex DFT and silicon debug challenges.

- Communication : Strong verbal and written communication skills for effective collaboration within cross-functional teams.