Job Description :

We are looking for skilled Design for Test (DFT) Engineers with 38 years of experience to join our growing team. The ideal candidate should have strong expertise in DFT architecture, implementation, and validation for complex SoCs.

Key Responsibilities :

- Develop and implement DFT architectures (Scan, MBIST, LBIST, Boundary Scan)

- Work on scan insertion, ATPG pattern generation, and fault coverage analysis

- Collaborate with design and verification teams for testability improvements

- Perform DFT verification and debug of test patterns

- Handle silicon bring-up, debug, and yield improvement activities

- Ensure high-quality test coverage and optimize test time

Required Skills :

- Strong hands-on experience in Scan, ATPG, MBIST, LBIST

- Good knowledge of DFT tools like Tessent / Modus / Encounter Test

- Experience in JTAG / Boundary Scan (IEEE 1149.1)

- Understanding of SoC architecture and digital design concepts

- Scripting knowledge in Perl / Python / Tcl

- Experience in debugging silicon issues is a plus

Qualifications :

- Bachelors / Masters degree in Electronics / VLSI / Electrical Engineering

- 3 to 8 years of relevant industry experience

Preferred :

- Experience with low-power DFT techniques

- Exposure to advanced nodes and large SoC designs