Posted on: 12/05/2026
Job Description :
Job Responsibilities :
- Define and implement DFT strategy for hierarchical designs, including Scan and ATPG.
- Execute ATPG, analyze scan coverage, debug issues, and drive design fixes to improve quality and coverage.
- Perform scan verification at both RTL and gate level.
- Prepare scan patterns, test content, and deliverables for Silicon Engineering execution.
- Debug scan patterns on ATE/testers as per project requirements.
- Collaborate closely with Design, Verification, and Physical Design teams to ensure DFT requirements are met and dependencies are aligned.
Minimum Qualifications :
- Bachelors degree in Electrical Engineering, Computer Engineering, or related field (or equivalent practical experience).
- Proven experience across multiple projects in DFT scan design and verification.
- Strong understanding of DFT methodologies, ASIC DFT synthesis, simulation, and verification flows.
- Minimum 4 years of hands-on experience in ATPG.
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Posted by
Naveen Meena
Last Active: NA as recruiter has posted this job through third party tool.
Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1635002