Experience : 68 Years

We are looking for an experienced DFT Engineer to implement and validate Design for Test structures for complex ASIC/SoC designs, ensuring high fault coverage and manufacturing test quality.

Key Responsibilities :

- Implement end-to-end DFT methodologies for ASIC/SoC designs

- Perform scan insertion and scan chain validation

- Develop and support BIST / MBIST architectures

- Generate and analyze ATPG patterns and fault coverage reports

- Execute pattern validation (with and without timing)

- Perform DFT debug and failure analysis

- Work closely with RTL, Verification, and Physical Design teams

- Ensure DFT signoff readiness before tape-out

- Improve test coverage, test quality, and test cost optimization

Technical Skills Required :

- Strong experience in Scan design techniques

- Hands-on expertise in :

1. BIST (Logic BIST)

2. MBIST (Memory BIST)

3. ATPG (Automatic Test Pattern Generation)

4. Pattern Validation

- Strong understanding of DFT insertion flow

- Experience in DFT timing analysis and constraints

- Knowledge of fault models (stuck-at, transition, bridging faults)

Additional Skills :

- Good understanding of SoC architecture and scan architecture

- Exposure to DFT signoff flow and coverage metrics

- Knowledge of debugging scan chain issues

- Understanding of test compression techniques (optional but good to have)

Collaboration :

- Work closely with RTL designers for scan insertion

- Coordinate with Verification teams for pattern validation

- Support Physical Design and STA teams for timing closure

- Interface with Test Engineering teams for silicon validation

Role Summary :

- DFT Engineer responsible for implementing scan, BIST, MBIST, ATPG, and pattern validation flows to ensure high-quality, testable ASIC/SoC designs with optimal fault coverage.