Job Description :

Key Responsibilities :

- Lead end-to-end DFT architecture, implementation, and signoff for SoC/IP programs.

- Define and own DFT strategy : Scan architectures, JTAG / iJTAG, BSCAN, ATPG, MBIST.

- Review and approve DFT plans, test architectures, and coverage targets.

- Drive ATPG, MBIST, and DFT simulation flows and signoff quality.

- Lead silicon bring-up, debug, and yield improvement from a DFT perspective.

- Manage and mentor a team of DFT engineers (task allocation, reviews, technical guidance).

- Conduct design and DFT reviews with stakeholders (Design, PD, Validation, Product).

- Drive schedule, risk management, and delivery commitments for DFT milestones.

- Establish and improve DFT methodologies, best practices, and automation.

- Interface with customers/management on DFT status, issues, and plans.

Required Technical Skills :

1. Strong hands-on experience in :

- JTAG / iJTAG, BSCAN.

- Scan architectures (full scan, compression, hierarchical DFT).

- ATPG (stuck-at, transition, at-speed).

- MBIST and memory test strategies.

- DFT simulation and debug (RTL and gate-level).

2. Solid understanding of SoC test architecture, test coverage, and test quality metrics.

3. Experience with industry DFT tools (Synopsys / Cadence / Siemens or equivalent) Tessent.