Description :

Job Title : DFT (Design for Test) Engineer

Location : Bangalore, India

Experience : 8 - 12 years

Job Overview :

We are looking for an experienced DFT Engineer with strong expertise in scan insertion, ATPG, and post-silicon validation. The ideal candidate will have hands-on experience with industry-standard tools like Synopsys or Tessent and the ability to quickly understand large-scale design architectures to contribute effectively from day one.

Key Responsibilities :

- End-to-end scan chain insertion and ATPG pattern generation.

- Post-silicon validation and fault coverage analysis.

- Work on large design architectures and provide immediate technical support for DFT activities.

- Collaborate with design, verification, and manufacturing teams to ensure testability and fault-free designs.

- Utilize Synopsys or Tessent toolsets for DFT implementation and analysis.

Technical Skills :

- Strong hands-on experience in SCAN and ATPG methodologies.

- Expertise with Synopsys DFT tools or Tessent suite.

- Ability to quickly understand and navigate complex SoC/ASIC architectures.

- Knowledge of fault models, test coverage, and test insertion flow.

Qualifications :

- Bachelors or Masters degree in Electronics, VLSI, or related field.

- 8 - 12 years of experience in DFT/Design-for-Test in VLSI domain.

- Strong analytical, problem-solving, and debugging skills.

- Excellent communication skills to collaborate across teams.

Why Join Us :

- Opportunity to work on cutting-edge SoC and ASIC designs.

- Exposure to end-to-end DFT flow from RTL to post-silicon validation.

- Collaborative work environment with experienced engineering teams.