Design Verification Engineer - SoC/UVM

Description :

Key Responsibilities :

- Design and implement advanced verification environments using SystemVerilog and UVM (Universal Verification Methodology).

- Develop reusable and scalable UVM testbenches for complex SoC and IP verification.

- Create modular and configurable verification components including :

- Drivers

- Monitors

- Scoreboards

- Checkers

- Coverage collectors

- Ensure compliance with verification standards and maintain verification infrastructure.

2. Simulation Infrastructure Development :

- Develop and maintain simulation infrastructure using SystemVerilog and C/C++.

- Write low-level software components using ARM or RISC-V Assembly for processor verification.

- Build test infrastructure that supports functional, regression, and performance testing.

3. SoC-Level Verification :

- Perform SoC-level verification of complex multi-core processor designs.

- Validate interactions between processor cores, memory subsystems, peripherals, and bus fabrics.

- Collaborate with RTL design teams to ensure design correctness and functionality.

- Identify and debug issues across the entire SoC architecture.

4. Verification Planning & Coverage Analysis :

- Develop comprehensive Verification Plans based on design specifications using tools such as vManager.

Define coverage metrics including :

- Functional coverage

- Code coverage

- Assertion coverage

- Monitor verification progress and ensure coverage targets are met.

5. Test Development & Random Verification :

- Develop random constrained tests to validate multiple use cases and corner-case scenarios.

- Ensure verification environments cover all customer use models and product requirements.

- Develop and maintain directed and random test scenarios for design validation.

6. Assertions & Coverage Implementation :

- Create and implement SystemVerilog Assertions (SVA) to validate design behavior.

Develop :

- Cover groups

- Assertions

- Checkers

- Protocol monitors

- Implement automated reporting mechanisms for tracking verification results.

7. Regression Management :

- Configure and run regression testing environments to validate design changes.

- Automate regression runs and generate detailed regression reports.

- Debug failing test cases and collaborate with design teams to resolve issues.

8. Mixed-Signal Verification :

- Develop verification environments for mixed-signal designs and sub-circuits.

- Apply advanced simulation techniques to improve simulation efficiency and accuracy.

- Use Real Number Modeling (RNM) techniques for high-level modeling of analog behavior.

9. Full Product Development Participation :

Actively participate in all stages of product development, including :

- Specification analysis

- Circuit design understanding

- Modeling and simulation

- Verification and validation

- Design for test (DFT)

- Silicon debug and bring-up

- Collaboration & Debug

- Work closely with design, architecture, and physical design teams.

- Debug complex issues in simulation and post-silicon environments.

- Provide feedback to improve overall design quality and verification efficiency.