Design Verification Engineer - SoC/ASIC

We are looking for a highly skilled Design Verification Engineer with 4- 8 years of experience in SoC/ASIC verification. The ideal candidate will have strong expertise in SystemVerilog, UVM, and functional coverage closure, along with experience in high-speed interface verification. You will be responsible for creating verification plans, test benches, and test cases to ensure first-time-right silicon.

Key Responsibilities :

- Understand the design and architecture requirements and create or modify test plans.

- Develop test benches and test suites using SV/UVM, C, or other relevant languages.

- Collaborate closely with the design team to identify and resolve design errors.

- Perform initial debug of test failures and analyze logs and waveforms for issues.

- Write assertions and functional coverage points, and create test sequences to cover them.

- Conduct regressions, triage test cases, and optimize coverage.

- Continuously improve verification quality by identifying coverage gaps and enhancing test scenarios.

- Automate the verification environment to support multiple design configurations.

- Track and report verification metrics/status as defined by the verification lead or manager.

- Support verification sign-off and tape-out readiness.

Required Technical Skills :

- Strong understanding of SoC architectures and IP-level verification.

- Hands-on experience in test case, assertion, and functional coverage planning.

- Proficiency in SystemVerilog, UVM, and C for test case development.

- Experience in developing test bench components from scratch.

- Solid experience in functional and code coverage closure.

- Expertise in AMBA protocols.

- Experience with high-speed interfaces such as PCIe 4/5, LPDDR 4/5, GDDR6, SD/eMMC, and Gigabit Ethernet.

- Knowledge of CPU-based/BFM(VIP) verification.

- Experience with boot, reset, clocking, debug, and low-power verification.

- Experience in performance verification and test optimization.

- Strong scripting knowledge : Python, Perl, Make, or similar tools.

- Hands-on experience with EDA simulation and waveform tools.

Desired Attributes :

- Strong debugging and problem-solving skills.

- Detail-oriented with a focus on quality and first-pass success.

- Ability to work independently and as part of a cross-functional team.

- Excellent communication and collaboration skills.