Description :

Role : Design Verification Engineer

About the organization :

QFocus AI Pvt. Ltd. (QFAI), a wholly owned subsidiary of QFocus Technologies LLC, is a consulting-led engineering services company with sharp focus on supporting next gen advanced products development across AI/ML, Compute, Communication, Storage and Consumer Electronics. Our mission is to help our customers deliver cutting-edge products on time ensuring world-class quality.

Why Join QFAI : Join a passionate team, dedicated to making a difference.

We are a close-knit team, with strong mission, vision and values that guide our day-to-day. Recognition of work, respect, and our multicultural community are key aspects of the employee experience and contribute to our continued success. Would you like to be part of our story? Don't hesitate, come and join us!

About this opportunity Design Verification Engineer :

We are seeking a highly skilled and passionate Design Verification Engineer to join our team working with the best in the Industry, developing innovative ASIC solutions for data center and AI Infrastructure.

As a design verification engineer, you will lead end-to-end design verification by creating verification plans, building test benches, and driving closure through functional and code coverage.

Collaborate across design, modelling, emulation, and validation teams to ensure robust debug, high quality, and complete verification.

Key Responsibilities :

- Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification

- Develop functional tests based on verification test plan

- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

- Debug, root-cause and resolve functional failures in the design, partnering with the Design team

- Review specifications, contribute to architecture discussions, and ensure verification completeness.

Required Skills :

- Experience in

- Revision control systems like Mercurial (Hg), Git or SVN

- Architecting and implementing Design Verification infrastructure and executing the full verification cycle

- Development of Universal Verification Methodology (UVM) based verification environments from scratch

- Verifying ARM/RISC-V based sub-systems and SoCs

- Verifying CPU/GPU designs

- One or more of the following areas : SystemVerilog Assertions (SVA), Formal, and Emulation

- Standard protocols (PCIe, AMBA, DDR, etc.) is a plus.

Education :

- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.

Experience :

- 5+ years of hands-on experience in SystemVerilog / UVM methodology

- 5+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments