Job Title : Design Verification Engineer VLSI

Location : Bangalore, India

Experience : 4 to 12 Years

Employment Type : Full-time / Permanent

About the Role :

We are seeking highly skilled and motivated Design Verification Engineers to join our VLSI engineering team.

The ideal candidate will have hands-on experience in functional verification of complex SoCs, IPs, or subsystems using industry-standard verification methodologies such as UVM/OVM.

You will be responsible for ensuring design correctness, performance, and quality through comprehensive verification planning, testbench development, and simulation.

Key Responsibilities :

- Develop and execute functional and constrained random verification testbenches using SystemVerilog (SV) and UVM/OVM methodologies.

- Create verification plans, define coverage goals, and drive coverage closure.

- Work closely with RTL design, architecture, and firmware teams to understand design specifications and derive test scenarios.

- Develop testbench components drivers, monitors, scoreboards, and checkers.

- Debug and resolve functional and performance issues using industry-standard simulators.

- Analyze and report code coverage, functional coverage, and verification metrics.

- Participate in design and verification reviews, ensuring completeness and quality of verification deliverables.

- Collaborate across global design teams to ensure seamless integration and timely delivery.

Required Skills & Qualifications :

- Strong hands-on experience in Design Verification using SystemVerilog and UVM methodology.

- Solid understanding of SoC / IP level verification, including interfaces such as AXI, AHB, APB, PCIe, DDR, USB, Ethernet, etc.

- Strong debugging skills using waveform viewers and simulation tools.

- Proficiency with EDA tools such as Synopsys VCS, Cadence Xcelium, or Mentor QuestaSim.

- Good understanding of RTL design concepts, simulation, and timing constraints.

- Experience with test planning, coverage-driven verification, and assertion-based verification (SVA).

- Scripting knowledge in Perl, Python, or Tcl for automation.

- Excellent problem-solving, analytical, and communication skills.

Good to Have :

- Experience in SoC integration verification and low-power verification (UPF/CPF).

- Exposure to emulation/FPGA prototyping and post-silicon validation.

- Familiarity with Verification IP (VIP) integration and random stimulus generation.

- Knowledge of formal verification techniques.

- Experience in functional safety (ISO 26262) or automotive/AI/networking domains is a plus.