Design Verification Engineer

Job Title : Design Verification Engineer / Senior Design Verification Engineer

Location : Bangalore

Experience : 5 - 12 years

Employment Type : Full-time

Department : Digital SoC / IP Verification

Role :

We are seeking highly motivated and experienced Design Verification Engineers with strong hands-on experience in SoC-level, Subsystem, and IP-level verification. The ideal candidate should have deep expertise in testbench architecture, UVM-based verification, and debugging complex test environments, along with proven skills in assertions, functional coverage closure, and regression management.

Required Skills & Experience :

Bachelor's or Master's degree in Electronics / Electrical / Computer Engineering.

- 5-12 years of experience in IP/Sub-System/SoC verification using SystemVerilog and UVM.

Key Responsibilities :

- Verification Architecture & Planning

- Develop and execute verification plans based on design and micro-architecture specifications.

- Define and implement testbench architecture and verification strategy for IP, subsystem, and SoC-level environments.

- Participate in verification reviews (test plans, coverage goals, sign-off criteria).

- Testbench & Environment Development

- Build UVM-based reusable verification environments from scratch.

- Develop and integrate testbench components (drivers, monitors, agents, scoreboards, reference models).

- Ensure scalability and configurability of the verification environment for multi-IP and SoC usage.

- Test Case Development & Debug

- Write directed, random, and constrained-random test cases in SystemVerilog/UVM.

- Debug simulation failures, identify design or testbench issues, and collaborate with RTL teams for resolution.

- Maintain regression infrastructure and triage failures to ensure daily stability.

Required Skills & Experience :

- Bachelor's or Master's degree in Electronics / Electrical / Computer Engineering.

- 5-12 years of experience in IP/Sub-System/SoC verification using SystemVerilog and UVM.

- Strong knowledge of UVM methodology, OOP concepts, randomization, and constraint management.

- Hands-on experience with :

1. Simulation tools : VCS, Questa, Xcelium, or Riviera

2. Debug tools : Verdi, DVE, SimVision

3. Coverage tools : VCS, IMC, UCDB-based coverage flows

4. Scripting : Python, Perl, Shell, or TCL for automation

- Experience with bus protocols (AXI, AHB, APB, PCIe, etc.).

- Solid understanding of assertion-based verification and coverage-driven verification.

- Familiarity with regression automation, version control, and continuous integration flows.