- Develop and maintain UVM/SystemVerilog verification environments for IP and SoC designs.

- Write and execute directed and constrained-random testbenches to validate design functionality.

- Create and maintain coverage models (functional and code coverage) to ensure design completeness.

- Collaborate with RTL designers to identify and debug design issues.

- Participate in review meetings, define verification plans, and track verification progress.

- Perform integration and regression testing of IP blocks and subsystems.

- Contribute to verification methodology improvements and automation.

Required Skills & Experience :

- 5 years of experience in RTL verification of IP/SoC designs.

- Strong knowledge of SystemVerilog, UVM, and assertions (SVA/PSL).

- Hands-on experience with verification tools like Synopsys VCS, Cadence Incisive, or Mentor Questa.

- Solid understanding of digital design concepts and RTL verification methodologies.

- Experience with functional coverage, constrained-random verification, and debugging.

- Strong analytical, problem-solving, and collaboration skills.