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Design Verification Engineer

M Systems
Multiple Locations
10 - 25 Years

Posted on: 21/09/2025

Job Description

- 15+ years of experience in System Level verification using C and UVM verification

- Proficient in testplanning and testcase development in C/Assembly/SystemVerilog

- Expertise in verifying design at RTL level and gate-level simulation

- SoC exp should have.

- Good understanding of coverage analysis, performance verification and use-case verification

- Usage of the third party Verification IPs

- Experience in functional test development for post-silicon bring-up/debug

- Fluency with scripting languages (e.g., Make, Perl, Python, Shell); and

- Has worked on the project complete cycle from the Specification to Tapeout and involved in Post Silicon Validation.

- Exposure to the FPGA Validation and debug

Must have experience on SoC verification and high-speed protocols exp. Like, PCIe, USB, GPIO, Slow Peripherals





Job requirements - Soft Skills

Communication

- Able to abstract technical details. Open to communicate with people on and off site. Open-minded.

- Excellent communication skills, enjoys working in an international team across locations

- Very good level of spoken and written English ( at least B2 level).

- Strong presentation and listening skills are required Team player

- Committed to the team and task

- Helping team members, sharing knowledge Self-driven and highly motivated

- Self-motivated and self-dependent worker. Embracing the task.

Highlight potential issues

- Regular reporting. Clean and organized working style. Able to go the extra mile Solution oriented attitude, pragmatic. Good problem solving skills

- Following and improving processes

- Able to follow corporate reporting standards Organized, trusted, committed to a long term employment

- Quality awareness

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