Design Lead - ASIC/RTL

Description : ASIC RTL Design Lead - 8+ / 10+ Years Experience

Location : Bangalore

Job Overview :

We are looking for a highly experienced ASIC RTL Design Lead to drive microarchitecture definition and RTL development for complex ASIC/SoC designs. The ideal candidate will have strong hands-on expertise in translating system requirements into robust hardware architecture, defining clean hardwaresoftware interfaces, and delivering high-quality RTL for high-performance, low-power designs.

This role requires technical leadership, ownership of critical IP blocks, and close collaboration with architecture, verification, firmware, and physical design teams.

Key Responsibilities :

- Lead microarchitecture definition and RTL development from high-level system and product requirements

- Translate design specifications into efficient, scalable hardware architectures

- Define and document hardwaresoftware interfaces, registers, and configuration models

- Design and implement RTL for complex IP blocks with focus on performance, power, and area

- Own RTL quality including code reviews, lint, CDC, and basic formal checks

- Interface with verification teams to ensure complete functional and coverage signoff

- Work closely with systems, firmware, and physical design teams throughout the development cycle

- Support timing, power, and area optimization for large-scale designs

- Mentor junior engineers and provide technical guidance across the design team

- Act as a technical point-of-contact for delivery milestones and design reviews

Required Skills & Experience :

- 8+ to 10+ years of hands-on experience in ASIC RTL design and microarchitecture

- Strong proficiency in Verilog and SystemVerilog

- Proven expertise in :

1. Microarchitecture development from design requirements

2. Defining clean and efficient HWSW interfaces

- In-depth understanding of MIPI protocols, including :

1. MIPI CSI (Camera Serial Interface)

2. MIPI DSI (Display Serial Interface)

- Hands-on experience designing video and audio IP blocks

- Strong understanding of high-speed, pipelined architectures

- Experience designing low-power RTL using clock gating, power-aware design techniques

- Familiarity with industry-standard EDA tools and ASIC design methodologies

- Ability to independently own complex design blocks from concept to RTL freeze

Preferred / Nice-to-Have Skills :

- Experience with multimedia pipelines (ISP, display, codec, audio processing, etc.)

- Familiarity with low-power standards (UPF / CPF)

- Exposure to SoC-level integration and system validation

- Understanding of timing closure and physical design constraints

- Prior experience as a technical lead or module owner

Location : Bangalore