Design & Verification Manager - System Verilog

Designation : DV Manager

Position : Permanent

Location : Bangalore / Hyderabad

Mode : Work from office

Experience : 8+ Years

Role Summary :

The DV Manager will lead end-to-end functional verification for complex IPs and SoCs. This role requires strong technical depth in SystemVerilog/UVM, hands-on verification experience, and proven people leadership.

The DV Manager will work closely with Architecture, RTL, Physical Design, DFT, and Program Management teams to ensure quality, schedule, and coverage goals are met.

Key Responsibilities :

- Own functional verification strategy for IPs and full SoCs

- Define verification plans, coverage metrics, and sign-off criteria

- Drive UVM-based testbench architecture (reusable, scalable, layered TBs)

Review and guide development of :

- Sequences, drivers, monitors, scoreboards

- Functional, code, and assertion coverage

- Ensure first-silicon success through robust verification methodology

Project Execution :

- Plan and track DV schedules, milestones, and risks

- Allocate tasks and balance workload across DV engineers

- Drive debug and root-cause analysis of complex RTL issues

- Collaborate with RTL designers to close functional gaps

- Participate in design reviews, verification reviews, and tape-out readiness reviews

Team & People Management :

- Lead, mentor, and grow a team of DV engineers

- Conduct technical reviews, performance evaluations, and skill development plans

- Hire and onboard DV engineers as per project needs

- Promote best practices, coding standards, and verification reuse

Cross-Functional Collaboration :

Work with :

- Architecture teams to understand specs and use-cases

- DFT teams for testability and coverage alignment

- Physical Design teams for verification closure support

- Firmware/Software teams for SoC bring-up and validation

- Support post-silicon debug and customer issue resolution when required

Required Skills & Qualifications :

Technical Skills :

- Strong expertise in SystemVerilog and UVM

- Hands-on experience with:

- IP-level and SoC-level verification

- Functional coverage, code coverage, assertions (SVA)

- Gate-level simulation (GLS) and low-power verification (UPF)

Solid understanding of :

- Digital design concepts (FSMs, pipelines, clocking, resets)

- SoC components: interconnects (AXI/AHB), memory subsystems, DMA

Experience with industry tools (any) :

- Synopsys VCS, Verdi

- Cadence Xcelium, SimVision

- Questa/QuestaSim

- Proven ability to lead and scale DV teams

- Strong problem-solving and debugging skills

- Excellent communication and stakeholder management

- Ability to work in fast-paced, multi-project environments

Good to Have :

- Experience in advanced nodes (7nm/5nm/3nm)

- Exposure to Formal Verification

- Experience with C/C++ testcases, Python, or SystemC

- Knowledge of RISC-V / ARM-based SoCs

- Prior experience in startup or high-growth semiconductor environments