BITSILICA - Senior Physical Design Lead/Manager - SoC/RTL

Key Responsibilities:

- Lead SoC/IP physical implementation through all stages of the RTL-to-GDSII flow for advanced nodes (7nm and below).

- Drive PPA (Power, Performance, Area) optimization at block and top levels.

- Own floorplanning, placement, CTS, routing, and signoff activities to meet design targets.

- Perform STA, IR/EM analysis, and integrate power intent using UPF.

- Ensure full physical verification (DRC/LVS) closure using industry-standard EDA tools.

- Manage ECO implementation, timing closure, and final tapeout preparation.

- Guide and mentor a team of physical design engineers; provide technical leadership throughout the project lifecycle.

- Work closely with RTL, DFT, synthesis, verification, and architecture teams to resolve cross-functional issues.

- Prepare project plans, track execution, and ensure delivery milestones are met.

- Identify and implement flow improvements, automation, and best practices for efficiency.

Required Skills & Experience:

- Strong hands-on experience in RTL-to-GDSII flow at advanced process nodes (7nm, 5nm, 3nm preferred).

- Expertise in floorplanning, placement, CTS, routing, and signoff methodologies.

- Proficiency in:

- STA (Static Timing Analysis)

- IR/EM analysis

- Physical verification (DRC/LVS)

- Power analysis

- Hands-on experience with leading EDA tools such as:

- Cadence Innovus

- Synopsys PrimeTime

- Mentor/Siemens Calibre

- Strong scripting skills in TCL, Perl, Python for flow automation.

- Experience with UPF for power intent implementation.

- Solid understanding of SoC architecture and block/top-level implementation practices.

- Excellent problem-solving, communication, and team leadership skills.

Preferred Qualifications:

- Prior experience leading multiple successful tapeouts.

- Knowledge of advanced packaging, multi-die integration, or chiplet-based design.

- Exposure to cloud-based EDA workflows.