JD : ASIC/SoC RTL Engineer/Lead/Digital Design

Experience : 7-20 Years

Mode : Full Time with Our Client

Location : Pune, Hyderabad,Bangalore, Chennai

NP : Immediate-90days

Role : ASIC RTL Engineer / Digital Design

Exp : 7 +

Mandatory Skill :

- RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory

- PCIe/DDR/Ethernet - Any One

- I2C,UART/SPI - Any One

- Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One

- Scripting languages like Make flow, Perl ,shell, python - Any One

Good to have :

- processor architecture / ARM debug architecture

- debug issues for multiple subsystems

- create/review design documents for multiple subsystems

- Able to support physical design, verification, DFT and SW teams on design queries and reviews

Details JD :

- Expertise in SoC subsystem/IP design

- Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog

- In depth knowledge on RTL quality checks (Lint, CDC)

- Knowledge of synthesis and low power is a plus

- Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)

- Good understanding of timing concepts

Knowledge of one or more of the interface protocols :

1. PCIe

2. DDR

3. Ethernet

4. I2C, UART, SPI

Expertise in setting up and using tools like :

1. Spyglass Lint/CDC

2. Synopsys DC

3. Verdi/Xcellium

- Understanding of scripting languages like Make flow, Perl ,shell, python etc

- Understanding of processor architecture and/or ARM debug architecture is a plus

- Able to help and debug issues for multiple subsystems

- Able to create/review design documents for multiple subsystems