ASIC RTL Design Lead - Embedded System

Role : ASIC RTL Design Lead

Experience : 7 - 15 Years

Location : Bangalore / Noida

We are looking for an experienced ASIC RTL Design Lead to drive end-to-end RTL design activities, micro-architecture definition, and chip-level integration for complex SoC designs.

Key Responsibilities :

- Drive end-to-end design execution from specification to synthesis-ready RTL

- Own block-level and chip-level integration activities

- Perform and guide RTL coding, review, and quality checks

- Ensure compliance with design guidelines, coding standards, and best practices

- Work closely with verification, physical design, and DFT teams

- Support debugging of functional and timing issues during integration

- Drive design closure including timing, area, and power optimization

- Participate in architecture discussions and technical decision-making

Technical Skills Required :

- Strong experience in Verilog / System Verilog RTL design

- Expertise in micro-architecture design and implementation

- Good understanding of :

1. Synthesis flow

2. Static Timing Analysis (STA)

3. Low power design techniques

4. Strong knowledge of CDC (Clock Domain Crossing)

5. Proficiency in Linting tools and design rule checks

Additional Skills :

- Understanding of performance, area, and power trade-offs

- Exposure to DFT concepts (Scan, BIST) is a plus

- Knowledge of industry-standard EDA tools

Leadership Requirements :

- Must have experience in leading RTL design teams

- Ability to mentor junior engineers and review technical work

- Strong technical ownership and project execution skills

- Experience in cross-functional collaboration with verification and PD teams