Delivering unrivalled edge AI solutions to accelerate and optimize real-time decision-making by powering smart edge devices and gateways that demand responsive AI computing at high energy efficiency.

Kinara is headquartered in Silicon Valley with development based in Hyderabad, India. Our name comes from the Hindi word for edge and reflects our commitment to our customers to build extremely innovative edge devices for retail, smart cities, industry 4.0, and automotive. In 2020, the company announced its first product, the Ara-1 Edge AI Processor. The product uses a polymorphic dataflow architecture. The Ara-2 was launched in December 2023 and is 5 to 8 times faster than its predecessor.

Work Location : Hyderabad

Who we are :

Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz

What we do :

Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and Kinara is looking forward to playing a significant role in it.

About the Role :

Kinara focuses on edge AI technology, committed to pushing the boundaries of whats possible in machine learning and artificial intelligence. We develop state-of-the-art AI processors, on-chip high speed interconnects that deliver unmatched performance, power efficiency, and scalability to meet the demands of modern AI applications. We also work on high speed interfaces like DDR, PCIE, USB etc. We are seeking a highly skilled and motivated VLSI Design Engineer to join our dynamic team.

The ideal candidate will have a strong background in VLSI design, IP design, IP integration into SOC, Design Debug skills, synthesis, LEC, timing clean up, lint/CDC/CLP/UPF .This role involves working on cutting-edge semiconductor projects and requires a combination of technical expertise, problem-solving skills, and the ability to work collaboratively within a team environment.

This is what you are responsible for :

- Define micro-architecture and write detailed design specifications.

- Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog.

- Implement complex digital functions and algorithms in RTL.

- Create and execute detailed test plans to verify RTL designs.

- Optimize designs for power, performance, and area (PPA) constraints.

- Perform simulation and debugging to ensure design correctness.

- Work with verification engineers to develop test benches and validate RTL against specifications.

- Strong understanding of digital design principles and concepts.

- Proficiency in writing and debugging RTL code.

- Experience with synthesis, static timing analysis, and linting tools.

- Familiarity with scripting languages such as Python, Perl, or TCL for automation.

- Experience in any of processor subsystem design, interconnect design, high speed IO interface design.

Qualifications :

- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.

- 1+ years of experience in RTL design and verification.

- Proven experience with digital logic design using Verilog, VHDL, or SystemVerilog.

- Experience with simulation tools such as VCS, QuestaSim, or similar.

- Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus).

Work culture :

We at Kinara have an environment that fosters innovation. Our team has technology experts who understand the big picture and mentors who coach passionate professionals to work on the most exciting challenges. We share responsibilities in everything we do, where every point of view is valued. Join us! Now tell us your story.