Analog Layout Engineer - Physical Verification

Job Title : Senior Analog Layout Engineer VLSI

Location : Bangalore, India

Experience : 6 to 12 Years

Employment Type : Full-time / Permanent

About the Role :

We are looking for an experienced Analog Layout Engineer with a strong background in custom and analog/mixed-signal layout design for advanced process nodes.

The candidate will be responsible for the layout design, verification, and integration of analog, RF, and mixed-signal IPs, ensuring high performance, reliability, and manufacturability.

This role requires close collaboration with circuit designers, physical verification, and CAD teams to deliver first-time-right silicon.

Key Responsibilities :

- Perform layout design for analog and mixed-signal blocks, including amplifiers, bandgaps, PLLs, ADCs, DACs, regulators, SERDES, and other custom circuits.

- Execute floorplanning, device placement, routing, matching, and parasitic optimization.

- Ensure layout symmetry, shielding, guard rings, and ESD protection requirements are met.

- Conduct LVS, DRC, ERC, and parasitic extraction (PEX) to ensure layout sign-off compliance.

- Work closely with analog circuit design engineers to meet performance and area goals.

- Optimize layouts for low noise, high speed, power efficiency, and yield.

- Handle full-custom and semi-custom layout design for multiple technology nodes (e.g., 7nm, 16nm, 28nm, 40nm, 65nm).

- Collaborate with CAD and methodology teams to improve layout flow and efficiency.

- Manage project deliverables, maintain quality documentation, and support tape-out activities.

Required Skills & Qualifications :

- 6 to 12 years of hands-on experience in Analog/Mixed-Signal Layout Design.

- Strong proficiency with EDA tools such as Cadence Virtuoso, Assura, Calibre, and Mentor Graphics.

- Solid understanding of layout design principles, device matching, common-centroid techniques, and parasitic management.

- Experience with deep sub-micron technologies (preferably 7nm / 16nm / 28nm and below).

- Proven experience in LVS/DRC closure, PEX analysis, and timing / performance optimization.

- Good understanding of circuit design fundamentals and analog performance metrics.

- Strong collaboration skills with circuit and verification teams.