Key Responsibilities - AMS Verification

- Work in Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs.

- Hands-on experience with AMS simulation environments using Cadence, Synopsys, or Mentor tools.

- Solid understanding of analog and mixed-signal circuits, including - comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators.

- Strong knowledge of Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling.

- Experience in block-level and chip-level AMS verification, including top-level testbench development, self-checking testbenches, and regression suites.

- Exposure to SystemVerilog (SV) and UVM from an AMS perspective is a plus.

- Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation.

- Fluency with Cadence Virtuoso-based analog design flow, including schematic capture, simulator/netlist configuration, and SPICE simulation.

- Ability to extract, analyze, and document simulation results and present findings in technical reviews.

- Familiarity with test plan development, AMS modeling, and verification methodologies.

- Supporting post-silicon validation and correlating measurement data with simulations.

- Team-oriented, proactive, and able to contribute in a multi-site development environment.